The present invention relates generally to a semiconductor circuit and more particularly to a semiconductor circuit that can be used as a level shifter in a semiconductor device such as a non-volatile memory.
Level shifters or level translators are used to receive logic signals at one voltage range and produce logic signals having a higher voltage range.
Referring now to FIG. 7, a conventional level shifter is set forth in a circuit schematic diagram and given the general reference character 700.
Conventional level shifter 700 receives an input signal IN having a high logic level provided by a Vcc power supply and provides an output signals (BOUT and TOUT) that has a high logic level provided by a Vpp power supply. Both the input signal IN and output signals (BOUT and TOUT) have a low logic level at the ground potential. The Vpp power supply is provided by boosting the Vcc voltage using a booster circuit. In this way, conventional level shifter 700 receives an input signal having a voltage range between ground and Vcc and provides an output signal having a voltage range between ground and Vpp.
Conventional level shifter 700 includes p-channel MOS (metal-oxide-semiconductor) transistors (P101 and P102), n-channel MOS transistors (N101 and N102), and in inverter V101.
Transistor P101 has a source and a body (substrate or well) connected to the power supply terminal, a drain connected to output signal BOUT, and a gate connected to output signal TOUT. Output signal TOUT is a true output signal and output signal BOUT is a complementary output signal. Transistor P102 has a source and a body (substrate or well) connected to the power supply terminal, a drain connected to output signal TOUT, and a gate connected to output signal BOUT.
Transistor N101 has a source and a body (substrate or well) connected to ground, a drain connected to output signal BOUT, and a gate connected to receive input signal IN. Transistor N102 has a source and a body (substrate or well) connected to ground, a drain connected to output signal TOUT, and a gate connected to receive signal INB. Inverter V101 received input signal IN at an input and provides signal INB as an output.
Output signal TOUT is of the same logic level as input signal IN. Output signal BOUT has a logic level that is inverted with respect to input signal IN.
The operation of conventional level shifter 700 will now be described.
When input signal IN is low, transistor N101 is turned off and inverter V101 applies a high to the gate of transistor N102. Thus, transistor N102 is turned on and pulls output signal TOUT to ground. With output signal TOUT low, transistor P101 is turned on and pulls output signal BOUT to the power supply potential. With output signal POUT being at the power supply potential transistor P102 is turned off. Thus, when inputs signal IN is low, output signal BOUT is at the power supply potential (VPP) or high and output signal TOUT is at ground or low.
When input signal IN is changed from low to high, transistor N101 is turned on and inverter V101 applies a low to the gate of transistor N102. Thus, transistor N102 is turned off. With transistor N101 turned on, output signal BOUT is pulled low. As output signal BOUT is pulled low, transistor P102 is turned on and pulls output signal TOUT toward the power supply potential or high. With output signal TOUT being at the power supply potential transistor P101 is turned off. Thus, when inputs signal IN is high, output signal TOUT is at the power supply potential (VPP) or high and output signal BOUT is at ground or low.
If a level shifter is only to provide level shifting from the Vcc voltage to the Vpp voltage, then conventional level shifter 700 may be sufficient.
However, in some applications, a level shifter needs to provide level shifting from the Vcc voltage to the Vpp voltage during certain operations and not provide level shifting (keep the output signals supplied by the Vcc voltage) at all in other operations. One such application is in a flash memory where a Vpp voltage level may be applied to a memory cell in a write, but data may be read at the Vcc voltage level. It can be difficult to design a level shifter that can operate at the same switching speed for both voltage output levels (Vpp and Vcc). Problems for this case will now be discussed.
The conventional example provides a pull down with n-channel MOS transistors and a pull up with p-channel MOS transistors. When the p-channel MOS transistor is beginning to pull up an output signal, Vds greater than Vgsxe2x88x92Vtp in the p-channel MOS transistor, where Vds is the drain-source voltage, Vgs is the gate-source voltage and Vtp is the threshold voltage of the p-channel MOS transistor. With Vds greater than Vgsxe2x88x92Vtp, the p-channel MOS transistor operates in the saturation region.
Also, when the n-channel MOS transistor is beginning to pull down an output signal, Vds greater than Vgsxe2x88x92Vtn in the n-channel MOS transistor, where Vds is the drain-source voltage, Vgs is the gate-source voltage and Vtn is the threshold voltage of the n-channel MOS transistor. With Vds greater than Vgsxe2x88x92Vtn, the n-channel MOS transistor operates in the saturation region.
When in the saturation region the drain current Id of a MOS transistor is obtained by the equation:
Id=K(Vxe2x88x92Vt)2xc3x97W/L, where K is a constant obtained by the channel mobility and the dielectric constant of the oxide film, W is the channel width of the MOS transistor, and L is the channel length of the MOS transistor. V represents the value of the voltage applied between the gate and the source of the MOS transistor and Vt is the threshold voltage of the MOS transistor.
When conventional level shifter 700 has the Vcc supply applied to the power supply terminal, the voltage applied between the gate and the source of the p-channel MOS transistors (P101 or P102) is much lower than when conventional level shifter 700 has the Vpp supply applied to the power supply terminal. Thus, the drain current of the p-channel MOS transistors (P101 or P102 will be much lower when conventional level shifter 700 has the Vcc supply applied to the power supply terminal than when Vpp is supplied to the power supply terminal. If the transistor size (channel width Wp and Wn) of the respective transistors (N101, N102, P101, and P102) in conventional level shifter 700 are designed in accordance with the operation at the Vpp voltage, operating characteristics at the Vcc voltage may suffer.
In the n-channel MOS transistors (N101 and N102), the gate-source voltage (Vgs) does not change in accordance with which power supply (Vdd or Vpp) is connected to the power supply terminal and the drain current Id is the same for both cases. Therefore, the drain current of the p-channel MOS transistors is reduced when Vcc is supplied to the power supply terminal which makes the output signals (BOUT and TOUT) rise slower than when Vpp is supplied to the power supply terminal.
On the other hand, if the respective transistors in conventional level shifter 700 are optimally designed in accordance with Vcc being supplied to the power supply terminal, the n-channel MOS transistors may not be able to supply sufficient current to overcome the p-channel MOS transistors when Vpp is supplied to the power supply terminal. Therefore, when the output signal is changed from high to low, the p-channel MOS transistor, which is turned on, may not be quickly overpowered by the n-channel MOS transistor which can increase the high to low switching time of the output signal. With an increased high to low switching time, the p-channel MOS transistor stays turned on longer and current can flow through from the power supply terminal to ground which increases current consumption.
Also, conventional level shifter 700 may not be able to lower the level of an output signal to ground unless the channel width (Wn) of the n-channel MOS transistors have a large enough value to provide sufficient driving capabilities. As a result, voltage levels of the output signals (TOUT and BOUT) may not be at sufficient logic levels (power supply or ground).
Referring now to FIG. 10, a circuit schematic diagram of a conventional level shifter is set forth and given the general reference character 1000. Conventional level shifter 1000 is obtained by adding transistors (P111 and P112 and N111 to N116) to conventional level shifter 700. Transistors (P111 and P112) are p-channel MOS transistors and transistors (N111 to N116) are n-channel MOS transistors. Transistors (P111 and P112 and N111 to N116) have been added for the purpose of snap-back prevention and improvement in hot electron resistance.
The operation of conventional level shifter 1000 of FIG. 10 is substantially the same as the operation of conventional level shifter 700 of FIG. 7.
Transistors (P101 and P102) have a channel width Wp of 5.0 xcexcm and a channel length L of 1.2 xcexcm. Transistors (N101 and N102) have a channel width Wn of 240.0 xcexcm and a channel length of 1.2 xcexcm.
FIGS. 8 and 9 are waveform diagrams illustrating the relationship between the voltage level change of the inputs signal IN and the voltage level of the output signals (BOUT and TOUT) in the operation of conventional level shifter 1000. FIG. 8 illustrates the case where Vcc is applied to the power supply terminal. FIG. 9 illustrates the case where Vpp is applied to the power supply terminal. FIGS. 8 and 9 illustrate SPICE simulation results. In FIGS. 8 and 9, the axis of abscissa indicates time and the axis of ordinate indicates voltage levels of input and output signals. In FIGS. 8 and 9, Vcc=1.5 V and Vpp=10.0 V. FIGS. 8 and 9, illustrate results from three cases, a low Vt, a typical Vt, and a high Vt of transistors.
As illustrated in FIG. 9 (Vpp connected to power supply terminal), when the input signal IN transitions from low to high, the time difference between output signal BOUT going low and output signal TOUT going high is not great.
However, as illustrated in FIG. 8 (Vcc connected to power supply terminal), when the input signal IN transitions from low to high, the time difference between output signal BOUT going low and output signal TOUT going high is large.
This indicates that the driving ability of p-channel MOS transistors (P101 and P102) is insufficient when Vcc is applied to the power supply terminal. This is because the n-channel MOS transistors (N101 and N102) have been sized (Wn/L) in accordance with the case where Vpp is applied to the power supply terminal and the large Wn can make the drain capacitance large.
In view of the above discussion, it would be desirable to provide a semiconductor circuit such as a level shifter that may be capable of quickly providing level shifted output signals in response to an input signal when a power supply of Vpp is applied to a power supply terminal. It would also be desirable to provide a level shifter capable of quickly providing non-level shifted outputs in response to an input signal when a power supply of Vcc is applied to a power supply terminal. It would also be desirable to provide a level shifter having desired operations without increasing the channel width of a n-channel MOS transistor.
According to the present embodiments, a level shifter that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. A level shifter may include a transistor providing a controllable current path between a voltage terminal and an output signal based on a logic level of an input signal. Series connected transistors may provide a controllable current path between a voltage terminal and an output signal based on the logic level of an input signal. One of series connected transistors may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width may be adjusted in accordance with a mode of operation and a transition time of an output signal may be improved.
According to one aspect of the embodiments, a level shifter may include a first drive circuit coupled between a first power supply terminal and a first output node. A second drive circuit may be coupled between the first power supply terminal and a second output node. A third drive circuit may be coupled between a reference potential and the first output node. A fourth drive circuit may be coupled between the reference potential and the second output node. The first drive circuit may have a first effective drive circuit width and the second drive circuit may have a second drive circuit width. The first and second drive circuit widths may be adjusted in accordance with a voltage level of the first power supply terminal.
According to another aspect of the embodiments, the first drive circuit may include a first insulated gate field effect transistor (IGFET) having a first type conductivity and a second IGFET having the first type conductivity providing parallel current paths between the first power supply potential and the first output node. The first IGFET may have a control gate coupled to the second output node and the second IGFET may have a control gate coupled to the second output node. The second drive circuit may include a third IGFET having the first type conductivity and a fourth IGFET having the first type conductivity providing parallel current paths between the first power supply potential and the second output node. The third IGFET may have a control gate coupled to the first output node and the fourth IGFET may have a control gate coupled to the first output node.
According to another aspect of the embodiments, the third drive circuit may include a fifth IGFET having a second type conductivity. The fifth IGFET may have a current path coupled between the first output node and the reference potential and a control gate coupled to receive a first input signal. The fourth drive circuit may include a sixth IGFET. The sixth IGFET may have a current path coupled between the second output node and the reference potential and a control gate coupled to receive a second input signal.
According to another aspect of the embodiments, the first drive circuit may include a seventh IGFET having the first type conductivity. The seventh IGFET may provide a current path between the second IGFET and the first output node. The second drive circuit may include an eighth IGFET having the first type conductivity. The eighth IGFET may provide a current path between the fourth IGFET and the second output node. The current paths of the seventh IGFET and eighth IGFET may be enabled and disabled in accordance with the voltage level of the first power supply terminal.
According to another aspect of the embodiments, a control circuit may be coupled to receive the voltage level of the first power supply terminal and may provide a control signal to a control gate of the seventh IGFET and a control gate of the eighth IGFET.
According to another aspect of the embodiments, the control signal may enable the current paths of the seventh and eighth IGFETs when the voltage level of the first power supply terminal does not exceed essentially a predetermined potential and may disable the current paths of the seventh and eighth IGFETs when the voltage level of the first power supply terminal does not exceed the predetermined potential.
According to another aspect of the embodiments, the level shifter may be provided in a column decoder. The column decoder may select at least one column of memory cells arranged in a matrix of rows and columns of memory cells in response to an address value. The level shifter may operate at different voltage levels based on a data read operation or a data write operation.
According to another aspect of the embodiments, a level shifter may include a first drive current path coupled between a power supply node and an output node. A second drive current path may be coupled between the power supply node and the output node. The second drive current path may be enabled when the power supply node is at a first potential and disabled when the power supply node is at a second potential.
According to another aspect of the embodiments, the first potential may be lower than the second potential.
According to another aspect of the embodiments, the level shifter may be coupled to receive an input signal having a first logic level at essentially the first potential.
According to another aspect of the embodiments, an input signal may have a second logic level at essentially a ground potential.
According to another aspect of the embodiments, the level shifter may be included in a decoder circuit in a semiconductor memory device.
According to another aspect of the embodiments, the semiconductor memory device may be an electrically programmable non-volatile memory and the power supply node may be at the first potential during a read operation and at the second potential during a write operation.
According to another aspect of the embodiments, a semiconductor device may include a first mode of operation where a first power supply potential may be supplied to a power supply terminal and a second mode of operation where a second power supply potential may be supplied to the power supply terminal. A level shifter may provide a shift between the first power supply potential and the second power supply potential in the first mode of operation. The level shifter may include a first drive circuit coupled to provide a first current path between the power supply terminal and a first output node in response to a first logic level of an input signal. A second drive circuit may be coupled to provide a second current path between the power supply terminal and the first output node in response to the first logic level of the input signal when in the second mode of operation and may provide a high impedance path between the power supply terminal and the first output node in the first mode of operation.
According to another aspect of the embodiments, the first drive circuit may include a first IGFET coupled to provide a low impedance path between the power supply terminal and the first output node in response to the first logic level of the input signal and a high impedance path between the power supply terminal and the first output node in response to a second logic level of the input signal. The second drive circuit may include a second IGFET coupled to provide a low impedance path between the power supply terminal and the first output node in response to the first logic level of the input signal and a high impedance path between the power supply terminal and the first output node in response to the second logic level of the input signal.
According to another aspect of the embodiments, the second drive circuit may include a third IGFET coupled between the power supply terminal and the first output node in series with the second IGFET. The third IGFET may be coupled to provide a low impedance path between the power supply terminal and the first output node in the second mode of operation and a high impedance path between the power supply terminal and the first output node in the first mode of operation.
According to another aspect of the embodiments, the level shifter may include a third drive circuit coupled to provide a third current path between a reference potential and the first output node in response to the second logic level of the input signal.
According to another aspect of the embodiments, the level shifter may include a fourth drive circuit coupled to provide a fourth current path between the power supply terminal and a second output node in response to the second logic level of the input signal. A fifth drive circuit may be coupled to provide a fifth current path between the power supply terminal and the second output node in response to the second logic level of the input signal when in the second mode of operation and provide a high impedance path between the power supply terminal and the second output node in the first mode of operation.
According to another aspect of the embodiments, the first drive circuit may include a first IGFET coupled to provide a low impedance path between the power supply terminal and the first output node in response to the first logic level of the input signal and a high impedance path between the power supply terminal and the first output node in response to a second logic level of the input signal. The second drive circuit may include a second IGFET coupled to provide a low impedance path between the power supply terminal and the first output node in response to the first logic level of the input signal and a high impedance path between the power supply terminal and the first output node in response to the second logic level of the input signal. The fourth drive circuit may include a third IGFET coupled to provide a low impedance path between the power supply terminal and the second output node in response to the second logic level of the input signal and a high impedance path between the power supply terminal and the second output node in response to a first logic level of the input signal. The fifth drive circuit may include a fourth IGFET coupled to provide a low impedance path between the power supply terminal and the second output node in response to the second logic level of the input signal and a high impedance path between the power supply terminal and the second output node in response to the first logic level of the input signal.
According to another aspect of the embodiments, the second power supply potential may be generated by boosting the first power supply potential.